• Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?
    Hi Experts, I'm reading white paper for ARMv7 and ARMv8. but when i reading cache part and memory re-ordering, i have silly questions..... Suppose there are below instructions..   Core A:      STR R0...
  • Memory barrier when accessing strongly ordered memory
    Hello, From the armv7 architecture, it mentions that all memory accesses to strongly-ordered memory occur in program order. When switching from accessing the normal memory to strongly ordered memory...
  • Barrier Transactions - ACE Protocol
    Hi all., Can anyone please, help me out in understanding this Barrier Transactions concept in ace protocol. I find little difficult and confusing in understanding about domain boundary, bi-section boundary...
  • Barrier after access to memory mapped register?
    Hi, Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from...