• PL310 cache synchronization
    Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
  • L2 Cache(Pl310) initialisation sequence
    Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...
  • pl310 CACHE_ID register
    In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register. To translate this RTL to a revision information, it is stated that "RTL release 0x9...
  • The merit of data cache cleaning
    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message...
  • Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...