• In AMBA AHB, If EBT(early burst termination) is happened in address phase of a transfer then it's data phase will be driven or not?
    Hi,    I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.   Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its...
  • Without the IDLE transfer between the bursts, can the arbiter change the master?
    I have a problem about AHB 2.0, the circumstance is: The master send two burst without IDLE transfer, and the HBURST is INCR. So the arbiter can’t predict when the burst finishes. And the sequence of...
  • BURST option in AHB-to-AHB sync-up bridge
    Hello, I am looking at cmsdk_ahb_to_ahb_sync_up.v component with BURST option enabled. I wonder how the BURST transfers are treated by this AHB-to-AHB sync-up bridge in case of an ERROR response?...
  • AHB transfer on Cortex-M3
    Hi, I am running following code in Cortex-M3. asm(" MOV R1,#0xFF0"); asm(" MOVT R1,#0xFFFF"); asm(" MOV R4,#0xAA0"); asm(" MOVT R4,#0xAAAA"); //start address asm(" MOV R3,#0x0000...
  • What is the "Integer divide unit with support for operand-dependent early termination"?
    We are evaluating the CM33. The CM33 documentation mentions " Integer divide unit with support for operand-dependent early termination", what does it mean by "operand-dependent early termination"? Thanks...