• Juno DRAM device model
    Is there any pointer or an ARM-internal contact to ask about the DRAM device used in Juno board? It is 32-bit width, so simply I wonder if it is composed of 4 of 8-bit device or 8 of 4-bit device.
  • Cache ECC in Cortex-R5 & Event bus
    Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
  • DRAM address mapping on a Cortex-A72 ARMv8
    HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • Why Cortex-R5 Bus-ECC documentation different from Cortex-R7
    Hello Support, In the Cortex-R5 TRM [Section 9.1.1 -- Bus ECC -- Chapter is  Level Two Interface] I see the following statement: " It is possible that fatal, that is double-bit, ECC errors might cause...