• How to realise a dual-core "LOCK-STEP" Cortex-M7 at the integration level?
    Is here any detail information or integration guide? how to realise the compare logic ,only to compare the CM7 core interface?
  • Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
    Cortex-R5 and Cortex-R7 implement as Dual-Core Lock Step (DCLS), does the two core run inparallel?
  • AXI Locked Write and Lock Scope
    Hi All,        1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not...
  • Debugger-based Firmware Test Framework
    Hi all. I'm currently working on a Python-based framework for on-target firmware testing of firmware of Cortex-M MCU systems. The approach is heavily based on the use of the debug probe to perform...
  • How to test " Lock-Step " is working on Cortex-R5 ?
    Dear Forum, How to test " Lock-Step " is working on Cortex-R5? Please provide inputs on Testing this feature. Thanks, Ravinder Are