• shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • Difference between Sub regions and Overlapping Regions in MPU
    Hi Experts, In the Memory Protection Unit, what is the difference between Sub regions and the Overlapping regions ? What is the typical use case of the MPU and how it helps in building a quality software...
  • shareable attribute in armv8
    Hi Experts,                     I was going through the arm v8 mmu page table formation, when it's compared to arm v7 it is completely different. I could see how to set the different page attributes like...
  • shareability memory attribute
    Hi ARM experts,     For shareability attribute, have some confusions:     1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...
  • MPU config and memory attributes
    I want config STM32F746 MPU , In the ARM Cortex M7 generic user guide External RAM memory region (0x60000000 - 0x7FFFFFFF)(512MByte) has WBWA (write back write allocate) cache policy see this link ...