• Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • Cortex-A53 backward compatible with AXI-4 interconnect
    Hi, The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if...
  • Joined-up thinking: ARM's interconnect portfolio
    We all know that to get anywhere in life you need to have connections. A good connection will open the right doors for you and ensure that you reach your potential with the minimum of wasted energy. The...
  • Learn how to optimize your system interconnect
    What is the connection between rugby football, interconnect and performance analysis kits? There is a seemingly never-ending march towards smaller, cheaper and more efficiency in complex chip design,...
  • Traffic Mixes in Networking Infrastructure - Base Transceiver Station (BTS) with CCN Interconnects
    Introduction ARM recently announced the next in the family of CCN (Cache Coherent Network) solutions. Specifically we introduced the CoreLink CCN-508. A quick recap – CoreLink CCN-508 is a cache coherent...