• Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
  • Synchronization primitives, do I need CLREX?
    Hi all, I'm trying to understand the LDREX/STREX commands in an ARM Cortex M3 MCU to implement atomic access to various variables (the goal is to implement semaphores/mutexes or increment/decrement shared...
  • Development Board with Trace Options
    Hello All, We've been looking for a development/evaluation board for project with a Cortex-M processor that has also the Trace option (MTB or ETM). It can be M0+, M23, M3, M4, M33, M35 etc.. What we...
  • How to check PTM trace from the ETB without using JTAG or other adaptor
    Hello. Im using I.MX6 solox Board from NXP Cooperation. This I.MX6 solox has a Arm Cortex-A9 processor. What I am trying to do is Tracing PTM which will be stacked up in the ETB buffer....
  • Synchronisation Primitives and Exclusive Monitors
    Later versions of the ARM architecture, using the LDREX/STREX instruction family, use "Exclusive Monitors" for inter-processor synchronisation of Shared Memory. How are these Monitors ("Local" amd " Global...