• TCM arbitration hazard: Considerations for Firmware
    According to the ARM spec (ARM DDI 0460D section 8.4.4): TCM arbitration Each TCM port receives requests from the LSU, PFU, and AXI slave. In most cases, the LSU has the highest priority, followed...
  • Cortex-M3:Little endian
    Hi All, The cortex M3 in STM32F100xx devices stores in little endian format. Does this mean that even the memory locations which I see in KEIL window are in the little endian format? For eg: 0x20000AFF...
  • Cortex M3 - Conditions for IT folding
    Hi folks, Some weeks ago, I discover the mechanism of IT instruction folding supported by the cortex-M3. As mentionned in 'Cortex-M3 Devices Generic User Guide', "In some situations, the processor can...
  • Instruction timings - arm cortex m3
    I am using the following 3 assembly sections to read a memory mapped i/o to multiple registers and to read same i/o and save it ram respectively , on an ARM Cortex M3. I want to know exactly how many...
  • Addressing memory question for Cortex-M3
    First I apologize if I am in the wrong place to ask this but can't find info anywhere or I just don't know what question to ask regarding memory address for the Cortex-M3. I am very new to microcontrollers...