• DWT instruction address
    Hello there, As I was reading the arch TRM some doubts emerged in the DWT component. When it talks about instruction address watching I am not sure if this refers to the address of the instruction...
  • Memory profiling (ARM Musca A1 Board)
    Hey ! So, I am trying to know how much bandwidth each memory of my system has. From what I have searched, the STREAM benchmark is the most recommended. The only problem is that I am using a resource...
  • Cortex M33 Multicore Boot issue
    Hello there! As I am exploring the Arm Musca A1 board in a multicore scenario, some doubts emerged. When I load each core program to the FLASH memory and then boot it up, each core loads it's own code...
  • Cortex M3 : what determines the cycle count for a variable cycle count instruction?
    I have looked at the cycle counts for the Cortex M3 instructions at http://infocenter.arm.com/help/topic/com.arm.doc.100165_0201_00_en/ric1414056333562.html . Some instructions are listed as taking a...
  • What conditions would generate the CM33 FPU underflow and input denormal exception flags?
    I am trying to understand the exception flags of the Cortex-M33 FPU and I am not able to understand what conditions would set the Underflow and Input Denormal flags. Can anyone provide the necessary...