• ACE VIP
    In ACE protocol we have multimasters , interconnect and main memory but I am not getting a clear picture of what my slave should be look like.So can you please help me out with the designing of the slave...
  • Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP
    Through a blog post by Jeff Defilippi , Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols ; you can request the the latest AMBA 5 specs through a link in that blog. These protocols...
  • Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)
    Hi folks, I've been working for years with ARM -M processors and I'm facing -A processors for the first time. I fell in love with Allwinner's V3S processor which is v7-A type. The datasheet says...
  • Secure SPI : STM32MP157-DK1 board
    Hey everyone, I am working on STM32MP157-DK1 with trustzone cortex-A. I want to use the SPI in secure side, but it's possible only with SPI 6 that is not mapped to the outside. It's possible to activate...
  • ARM Cortex A9 boot from spi-flash 32M
    Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However...