• Push/Pop in Cortex A55 64bit mode
    Hi, Is there any alternate instruction for push/pop since it is not supported in the cortex a55 (64 bit mode)? Currently I'm doing the stacking of the processor register manually using STP/LDP instructions...
  • Arm Cortex-A55: Efficient performance from edge to cloud
    Have you heard? There are a couple of new CPUs in town... and they pack a punch! Of course, I am talking about the Arm Cortex-A75 and Cortex-A55 , the first Cortex-A processors based on the recently announced...
  • What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?
    Hi experts, I do an experiment about cpu power with a board which has 4 cores of Cortex-A55. I try to power on/power off core1~3 parallelly. Sometimes Both PACCEPT and PDENY are zero after changes...
  • How can I get the number of non-cacheable access in CA-55?
    The PMU of CA-55 can not count non-cacheable access event. L1I_CACHE_ACCESS and L1D_CACHE_ACCESS does not count non-cacheable access. I want to distinguish cacheable access and non-cacheable access...
  • Data abort exception for unaligned access in Cortex A55
    Hi, I have written a simple assembly code in Cortex A55, which executes in EL3, 64-bit execution state. In the code, the cache and MMU is disabled which means that any memory accessed will be treated...