• Cortex-A9 Branch prediction to speculative execution
    Hi, I am building a cycle accurate simulator for the Cortex-A9 core, and so far I constructed most of the stages of the pipeline. However I am having trouble placing something that is not clear in any...
  • Speculative data fetching on ARMv7-M
    I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it. The only documentation I can find for it is a small section in ARM...
  • Speculative Branching.
    Hi, I am new to ARM Cortex M3 Microprocessors. Can somebody please explain me the speculative branching in layman terms. Thanks in advance.
  • Cortex-M pipeline, relationship prefetch and decode stages
    Hi ARM specialists, I have a question about Cortex-M series pipeline behavior. According to the page 15 of "ARM Cortex-M Programming Guide to Memory Barrier Instructions Application Note 321", it is described...
  • Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...