MMU and Cache configuration

Hello there, I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core. I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and...
Different between AF vs AP (MMU Setup)

What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
MMU: force identity mapping without pages?

hi, on a cortex a53, I would like to get the best of both worlds. Having dcache enabled but no page walk in case of a miss. I want no memory protection because we manage the whole system ( kind of...
Disabling the MMU

Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
How to design simple memory protection using MMU attributes & modes ?

Hello, Can anyone give some points as to how to design simple memory protection model, of standalone OS application composed tasks, each has its own region/section with attributes such as read only...