[ARMv7] question about writel & barrier

Hi Sirs, I got a question about the way Linux 3.18 defines the "writel()". In linux-3.18/arch/arm64/include/asm/io.h, it describes: /* * I/O memory access primitives. Reads are ordered relative to any...
armv7 instruccion set opcodes

hello, I am in a research project and need the assembler guide with opcodes of armv7 processor. I'm really looking manuals byte code assembler, not C language or C ++. I need the hex values of each instruction...
ARMv7 Branch Prediction Enable

On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0 @ Read Control...
Armv7 ICIALLU vs ICIALLUIS

Hi experts! I have a question about cache instruction. DDI0406C_b_arm_architecture_reference_manual for Armv7 says Effect of the Multiprocessing Extensions on All and set/way maintenance operations The...
Armv7 Store Buffer

Hi, Store Buffer holds store operation before it is commited to Cache or Main Memory. So only if the proper store buffer entry is drained, can we get the right data by a load operation. Am I right...