• Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM
    Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...
  • How to configure Cortex-A57 PMU
    I asked this question in a different community space but it seemed like this is a more appropriate home. I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The...
  • SIGILL in 32bit chroot on Cortex-A57
    I'm getting a SIGILL when running a ARMv6 program in a chroot environment. The instruction that triggers it is Program received signal SIGILL, Illegal instruction. 0x000104f0 in f () (gdb) disassemble...
  • does different arm TRM revisions also have changes in Hardware?
    Hi I have an inquiry. our company is using Cortex-A9 quad Core. So in ARM website there are many technical reference manuals for the same in different revisions , such as: r2p0 r2p2 r3p0 r4p0 r4p1 so...
  • Can we reset L2 subsystem for cortex-A57?
    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running...