Cortex-A9 TLB lockdown

Hello, expert. I tried to implement TLB lockdown in Cortex-A9. Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it. I tried TLB lockdown following Cortex...
Synchronization of caches on ARMv8

Hello, I have a question regarding the synchronization of caches on ARMv8 on Multi-Core. Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes...
is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

hi : I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*). however, I can not find any clue about flushing L2 cache to DRAM(if without L3). and I saw some points that...
Memory map for ARMv8-M TrustZone SOC's

Hello, I was wondering what the memory map of an SOC that includes a ARMv8-M TrustZone enabled system would like. Is it fixed or is it variable ? Based on the ARMv8-M ARM, it appears that things like...
Does ARMV8 has Cortex M series

Hi all, The new core ARM V8 supports A & R series alone M series are also be released in near future ? If not why ?