• Why the address width of MMU-500 is different with Cortex-A53/57?
    I find the description below from MMU-500 TRM. Address width The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address...
  • CoreLink CCI-500: exceedingly good (Infographic)
    It’s been a busy start to the year for ARM as the year kicked off with CES 2015 showcasing some of the amazing experiences the consumer electronics of today (and tomorrow!) can provide. We saw a lot of...
  • GIC-500 how connects to CPU cores?
    GIC-500 how connects to CPU cores? 在GIC-500 中CPU Interface 是GIC的一部分还是cluster 的一部分?
  • Disabling the MMU
    Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
  • MMU initialization for an ARM multicore system
    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib). On the shared SDRAM, I am planning to have dedicated...