• Unaligned accesses - CMSDK Example Cortex M0
    The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better. Does the...
  • CMSDK - design multi-master bus
    Wenkwei asked: "with the M3 designstart CMSDK, is it possible to design multi-master bus? In the IoT Cortex-M TRM, only an ahb-lite structure is illustrated. That document does mention AHB and APB expansion...
  • 10 Useful Facts about Cortex-M System Design Kit (CMSDK)
    The Cortex-M System Design Kit (CMSDK) is an extremely useful product for chip designers and FPGA designers working with the ARM Cortex-M processors. It contains a wide range of AMBA bus infrastructure...
  • Parallelism between CPU and FPU
    Hi. I have a question regarding Cortex-M4 processor with floating point unit. Is it somehow possible to do some computation in parallel in CPU (with integers) and FPU (with floats)? Probably not, because...
  • Basic Flash Programming and the process in integrating Cortex M0
    Hello Guys! I am Integrating Cortex-M0 with peripherals and memories. Previously I used Block ROM/RAM in FPGA where I just uploaded COE files to make it run. But now I want to use an external flash...