• Current priority level of processor
    Hi, I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the...
  • Get current active interrupt priority
    Hi everybody, We are working on a simple priority RTC (run to completion) framework for the Cortex M3/M4. Thanks to the NVIC/BASEPRI, we got most of this functionality for free but we want to extend it...
  • What happens if a same priority exception came while context-switch is executing?
    Hello, I meet a problem while using Spin Model Checker to verify a RTOS kernel based on Cortex-m3 platform. My PendSV is in the lowest priority 16 and perform to schedule next user task and context...
  • Yet another processor crash!
    Yes, my ARM cortex M3 is crashing, whats new? Well, after 3 weeks of debug  I am no closer to an answer, so I hope you will not mind if I list what I have tried and see if anybody has a flash of inspiration...
  • Changing interrupt priority to prevent nesting
    Hi, I'm working on M0+, but the question applies to M3 or M4 too. I have the following situation: 2 interrupt sources inject events on a state machine that must handle each event separately (not nested...