• Cortex-A8 Pipelined cache maintenance
    Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...
  • ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
  • Cache maintanance operation to PoC
    Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...
  • Cortex-A8/A15 L1 cache
    Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
  • ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...