• Power Management Options in Cortex A
    Hi Experts, Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers...
  • Confusion about exception level of ARMv8
    Hi, I am fairly new to ARM processor and start work with cortexA57 recently.  After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8. 1. How...
  • How to access the system control register?
    Hi all, I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation. ...
  • ARM cortext A53 Physical Address Flush
    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then...
  • Can we reset L2 subsystem for cortex-A57?
    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running...