• Overlapping the execution of VDIV.F32 and SDIV/UDIV
    The Cortex-M4F has separate hardware for integer and floating-point arithmetic. Both integer and floating-point divide instructions take up to 12 clock cycles to complete. I've verified that integer instructions...
  • Instruction width selection - forward/external reference
    Hi, I am learning the Thumb 2 instruction set and at the moment I am trying to understand when to use the instruction width specifier. e.g.: ldmia.w sp!,{r3,lr} I understand sometimes it is necessary...
  • What is P1, P2, P3 and P4 use in Thumb2 IF block instruction?
    Hi, When I read IT block in Thumb2 instruction, I don't understand the use of P1, P2, P3 and P4. From below pictures, can you tell me what use are P1, P2, P3 and P4? Thanks, This line is especially puzzling...
  • cortex-A15 instruction set and optimization ways on this platform?
    Dear, I am an greenhand developer on cortex-a15. now I need some specification as follows: where I can get the instruction set of cortex-A15? are there some documents about optimization technology on...
  • From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code?
    From the CPU's point of view, how does it distinguish an assembly code is an ARM code or a Thumb code? Is there some signal bit represent the code is ARM or Thumb code, this is just my guess.