• Initial page table walk for secure/nonsecure accesses
    I have a basic concept question. From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups. So these can...
  • How to set up stage-2 translation table
    Hi, I am trying to enable stage-2 translation for Armv8 aarch32, cortex-a53. If I set HCR.VM=1(enable stage-2 translation) it will crash. I suspect it does not set up stage-2 translation table. But...
  • dump MMU translation table for A9 in Linux
    Hello, I would like to know how to read the translation table info for A9 from embedded Linux. In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux...
  • Cortex-A53 - Understanding Translation Table (Cannot enable MMU)
    Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
  • translation table APTable permission problem
    Hello, I am trying to make pmd level of the translation table as read only so that any writes in the pte entries should cause a permission fault. Current steps which i am doing are: 1) inside...