• MMU - Permission Fault with EL1 access
    Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
  • Jetson TX2 cortex-a57 crash after enabling mmu
    My code is running at EL2 in one of the cortex-a57 cores in an nvidia tx2. The code is crashing just during initialization after I enable MMU. However, what I just found out is that this is only happening...
  • Enable MMU and d-cache on ARMv8 for u-boot
    Hi, This question is for MMU and d-cache. When I tried to enable MMU and d-cache for u-boot I ran into Synchronous Abort handler while writing to PCIe device registers which I mapped as uncached memory...
  • Different between AF vs AP (MMU Setup)
    What is different between AF & AP? I understand AP = permission access as read/write/readonly/no access but what is AF?
  • Trouble configuring MMU for 2MB block mapping
    So I'm working with QEMU and AArch64 mode and using the MMU. I've succesfully mapped 4K blocks, but I'm having trouble mapping 2M blocks. My configuration is such that the L1 entries are 1GB blocks, L2...