• how to understand ARMv8 exception level1 secure/non-secure MMU?
    Hi Experts ,      ARMv8 MMU TTBRn_ELx registers are banked by exception level.      In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1      and Non-secure...
  • Reason Behind EL2 in non-secured state ARMv8
    Hi Experts, What is the reason behind allowing EL2 only in non-secured state in ARMv8 ? Regards, Techguyz
  • Transition to secure monitor flow on ARMv8
    Hi everyone, Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is...
  • How to deice debug target exception level of watchpoint on ARMv8 architecture
    Hello, everyone I'm new to this community. I'd like to ask many questions and want to help someone. Now I have some difficulties in understanding aarch64's watchpoint exception handling scheme. I found...
  • Transition to secure monitor flow on ARMv8
    Hi everyone, Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is...