• Is it necessary to flush data cache of a modified page table entry?
    Dear experts, Q0) why can't MMU observe the table entry change made by its company core ? working for Cortex-A55MP, EL1 in Aarch32, svc mode: Both 2 level of table entry are attributed as (inner...
  • Why in A64 the coprocessor is removed?
    For the view of architecture, why the coprocessor is removed for A64 instruction set?
  • determine a page size on armv8
    Hi, I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of __asm__ volatile ("at s1e1r, %0" : : "r" (buf)); __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r"...
  • Why does ARM have 64KB Large Pages?
    The ARM720T user manual mentions small and large pages. Since the ARM 720T requires a 64KB page table entry to be duplicated 16 times in the page table, why not place 16 small page (4KB) entries to mimic...
  • aarch64 kernel using aarch32 page tables
    Hi ! I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8. My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point...