• Core_n System Timer reset behaviour
    Hello, I'm working with i.MX8DX (Dual Core CortexA35) My question is this: If a PE is reset. Is the CNTPCT_EL0 is also reset and start from 0? or keep counting normally?
  • System wide cache flush
    Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
  • How Can I Synchronize the Generic Timer values in different PEs in the same Core?
    Is the timer values in CNTPCT_EL0 in each PE in the same core are synchronized? and if not how can I do so?
  • What ARMv8.x revision Cortex-A35 is?
    Hi, ARMv8-A specification mentions revisions and options. I cannot find Cortex-A35 adheres to which exact version: ARMv8.1, 8.2, 8.3? I want to know which of the extensions described in the generic...
  • Priority Drop and Deactivation Interrupts at EL2
    Hello I'm working on the Bootloader stage (EL2), I'm trying to enable Interrupts with gic v3 in that stage I've enabled routing IRQ, FIQ and Aborts from EL0, EL1 and EL2 to EL2 using these piece of...