• MMU - Permission Fault with EL1 access
    Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
  • TTBR1 translation fault when using an identity mapping
    Hello everyone, I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3...
  • Configuring an interrupt source as FIQ at EL1
    For one of our devices (which uses ARM A53 Core with GICv2) we need to configure one of the interrupt sources as FIQ at EL1. So is there any support for doing such a thing preferably in any of the branches...
  • How to know why system hangs in EL2
    Hello, I am trying to enable stage 2 translation on Raspberry Pi 3B+. I create a translation table, store its base address in VTTBR, configure VTCR and HCR to enable stage 2 translation. These steps...
  • Which is better of thees CPUs
    Which is better of thees CPUs: Cortex A53 octa core 1.5 ghz, Cortex A7 Allwinner T8 Eight core 2.0 ghz, Cortex A9 Quad-Core 1.8 ghz ?