• Arm Cortex-A8 program flow prediction
    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code: char SecretDispatcher[256 * 512]; int counter = 0; //evicting SecretDispatcher from cache...
  • Arm Cortex-A8 program flow prediction
    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code: char SecretDispatcher[256 * 512]; int counter = 0; //evicting SecretDispatcher from cache...
  • ARMv7 Branch Prediction Enable
    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR  p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0     @ Read Control...
  • A question about octa-core
    For a octa-core soc design that contains two Cortex-A clusters and four cores per cluster, does any application require 3, 5 or 7 cores running at the same time?
  • Transition to secure monitor flow on ARMv8
    Hi everyone, Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is...