• Arm Cortex-A8 program flow prediction
    I am examining ARM-Cortex A8 flow prediction abilities, in order to done this i implemented below code: char SecretDispatcher[256 * 512]; int counter = 0; //evicting SecretDispatcher from cache...
  • Question about program flow prediction
    I am examining ARM Cortex-A8 program flow prediction abilities, in document of Cortex-A8 arm specified that it would predict LDM instruction with PC in register list. now i have a question, if we have...
  • ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
  • ARMv7 Branch Prediction Enable
    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR  p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0     @ Read Control...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...