• [ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload
    Dear Experts I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during...
  • How to configure Cortex-A57 PMU
    I asked this question in a different community space but it seemed like this is a more appropriate home. I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The...
  • Synchronization of caches on ARMv8
    Hello, I have a question regarding the synchronization of caches on ARMv8 on Multi-Core. Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • ARMv8-A: Virtual to physical translation sometime "fails"
    Hi I have a strange effect: I need to convert a virtual address to the physical one. In the current scenario, I have a 1:1 mapping, so I would not need it, but left the code: mov x3,x0 // for debug...