• Issue with ARM926EJS uboot relocation to DDR
    Hi All, I'm new to Uboot and has experience in bringing up VxWorks BSPs. I am working on developing support for a new SOC in Uboot. The SOC has an arm926ej-s based core and is implemented on Xilinx...
  • L2C-310 double linefill issuing
    Hi, I have a problem to understand the functionality of double linefill issuing. In which case the cache controller loads a second cache line from L3 into L2? Where is the difference to prefetch?...
  • SOFT Reset hangs sometimes in ARM926ej
    Hi, I am working on PC205 having ARM926ej as a processor in it along with DSPs included in it. Now, I am facing an issue regarding SOFTWARE REBOOT/RESET of the ARM processor as i don't have any WATCHDOG...
  • ARM926EJ-S, Can a STMIA result in four single accesses instead of a burst?
    Hello Community, I have a question regarding the STMIA instruction in an ARM926EJ-S. We build a SOC with this core and one of our own modules connected to the DATA-AHB has a bug. One workaround for this...
  • Setting up TCM Memory in ARM926EJ-S
    Note: This was originally posted on 20th October 2008 at http://forums.arm.com Hi all, I am currently trying to turn on TCM in ARM926EJ-S where there is 64K for ITCM, DTCM and internal SRAM. I have decided...