• How cortex-M4 handles data hazard situations in the pipeline?
    Hello to all, Since I am working on ARM Cortex-M4, I would like to know about the handling of the hazard situations (especially the RAW, WAR and WAW hazard situations) in the pipeline. Is the processor...
  • Does Cortex-M3/M4 continue with burst in response to ERROR?
    AMBA spec states that 'Master can choose whether to terminate current burst or continue with burst in response to ERROR'. What does Cortex-M3/M4 do in response to ERROR? Does it continue with burst in...
  • How does matrix4x2 implement in busmatrix?
    Hi, Currently I'm digging the bus matrix 4x2 bus matrix from But I have some question. How does the bus matrix4x2 implement in bus matrix? I just draw what I've understand it as the below ...
  • Addressing memory question for Cortex-M3
    First I apologize if I am in the wrong place to ask this but can't find info anywhere or I just don't know what question to ask regarding memory address for the Cortex-M3. I am very new to microcontrollers...
  • Cortex-M1 on Actel - how to start?
    Hello ARM Community, some time ago I started with Cortex-M1 core on Actel Proasic3L FPGA. I don't have much experience, but I have development board without working example:) I tried to follow Actel's...