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    Hi, I have question related to cortex M7 cache behavior. I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated...
  • ARM Cortex A9 - Enabling/Disabling the Caches
    Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
  • Cortex-M7 minimum schematic ?
    I'm looking to start a new design based on the ARM Cortex-M7 and have been reading thousands of pages of documentation ( not done yet of course ). I am able to design my own schematics and PCBs so I'm...
  • Cortex-M MPU limitations
    Hi All, The title may seem a bit negative, just from my personal point of view. What is the main reason of the two requirements of setting up MPU, namely size and start addresses of MPU regions. First...
  • Understanding XDMAC on Cortex-M7
    I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it...