• M0+ Stack Pointer (PSP/MSP) Clarification
    Background I'm working part-time on a Cortex M0+ based SoC converting a very processor-intensive section of C++ code (inner-loop executed 10s of 1000s of times a second & compiles to over 400 instructions...
  • What is the meaning of a 64 bit aligned stack pointer address?
    According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says: "Although the processor hardware allows SP to be at any word aligned address at function...
  • Break Points and Watch Points
    Greetings,                Sir,i am working on SWD, after  Research on Break Point & Watch Point i found One Thing That There are Some Comparators will Do These Things but I am not Very Sure That How These...
  • The reason why the exception frame forms on PSP?
    Hello experts, I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture. My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP...
  • MSP & PSP - 'Using it All'
    As I understand it, if, when my system boots and I switch to using PSP (process stack pointer) and allow the CPU to handle exceptions using MSP? Have I got that the right way around? The reason is that...