• Question about T3 and T4 encoding of B/Bcc (Branch) Instruction
    On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual... Do T3 and T4 really have the J bits of the immediate value in the...
  • Programming FPGA Block RAM connected to Cortex-M0 using JTAG
    Hi, I am connecting the BRAM inside FPGA with the Cortex-MO processor. Is it possible to program the BRAM using JTAG? The BRAM will act here as on-chip memory having the memory map of 0x00000000. I...
  • translational table : block and table descriptor
    Hello Experts, I am trying to understand in the attached snapshot, how the values of m and n are derived for table and block descriptors respectively ? Can anyone please explain me since I am...
  • Quickly creating audio designs on the Cortex-M4 using graphical blocks
    It is possible to design and generate production ready optimized code for the Cortex-M4 without having to create a single line of code! Come to the 50 minute presentation on Wednesday, Oct 30th at 1pm...
  • What is P1, P2, P3 and P4 use in Thumb2 IF block instruction?
    Hi, When I read IT block in Thumb2 instruction, I don't understand the use of P1, P2, P3 and P4. From below pictures, can you tell me what use are P1, P2, P3 and P4? Thanks, This line is especially puzzling...