• instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • why does LDR takes two cycle to be executed
    Hello everyone, I am currently working on a cortex-M0 microprocessor(LPC1114). I have looked through all the possible instruction descriptions but I did not find anyone of them explaining why some instructions...
  • Additional memory cycles during LDR with unaligned address
    When LDR makes an unaligned memory access on a Cortex-M4 (ARMv7), I would expect there to be two memory read cycles required to retrieve the data. More specifically, I would expect that to be true whether...
  • unaligned data fetch in Cortexa9
    I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
  • which is better for performance fetching instructions from flash or SRAM?
    Hello, If I copy the firmware to SRAM and start execute program from there using STM32F429 (which means that system bus is used to fetch instructions instead of I-code bus). At this case do fetching...