• ARM Cotex-M0 memory allocation for structure array with bitfeilds
    I want to use a structure as given below on my ARM Cortex-M0, I am using C programming. struct path_table_t { uint8_t lut_index; uint8_t flag : 1; }; 'flag' field is made to be single bit by bit fields...
  • Are any companies planning to release a Cortex-M7 IC with lock-step?
    Hi guys, I'm eager to use the M7 in ASILD and SIL3 applications as it offers our developers a more familiar environment and behaviour compared to the R series, amongst a few other preferential attributes...
  • Flash/RAM memory interfaces on Cortex-M7 based MCU for fast code execution
    Hi, experts! I would have few questions regarding Cortex-M7 and (in my case) STM32F7 MCU, if anyone here is familiar with them. I am not sure how to use MCU's different flash/RAM interfaces to gain maximum...
  • Cortex M7 SPI Interface Register Base Address
    Hello, I am trying to use the SPI interface on the Teensy 4.0 board which has a Cortex M7. I found the registers and there offsets in the RM0444 Reference Manual but can't find the Base Address of...
  • Cortex-M7 load instruction latency and pairing
    Hello, What is the latency for the LDR instruction when the result is used for integer arithmetic operations (for example DSP MAC instructions)? Also, can 64-bit loads (LDRD) be paired with another instruction...