• Using interrupts not implemented as Software interrupts?
    We know that a Cortex-M0 or any other Cortex-M may have fewer interruptions implemented the architecture defined in the standard, so we can not use interrupts implemented as software interrupts by manipulating...
  • Changing prio of running IRQ triggers hardfault
    Hello I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture...
  • MPU is not triggering MemFault or HardFault
    MPU is not triggering MemManage fault. I want to protect a memory region of 64 bytes starting from 0x20000000. I've configured the MPU registers accordingly, but when I write in a protected memory location...
  • Timer interrupts synchronization in Cortex M4
    Hi, I am working on Cortex M4 based Microcontroller. I have one timer(TIM0) running and when it gets restarted, GPIO pin is set. I have one more timer (TIM1) running separately and it sets another...
  • Cortex-M4 interrupt priority dynamically change while in ISR
    Hello, I am using STM32F407ZGT6 Cortex-M4 microcontroller. I am interested in changing the priority of a certain interrupt while servicing the same interrupt. Is that possible? More elaborately, lets...