• Efficient uasage of PLD instruction in combination with Load instructions?
    Hi all,  after a long time I'm back to forum with a question I'm posting this question with some pseudo code for(i=0;i<100;i++) { instruction1 instruction2 instruction3 ................. instructionA...
  • ARM Cortex A8 L2 Cache Flush Invalidate
    Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1");                                                  asm volatile ("smc #1...
  • Code for integer division on Cortex-A8?
    Hi all, when I wrote a C code with division operation the compiler is generating some library calls.....when I tried to see the equivalent code for those function calls...I'm unable to reach there (may...
  • Cortex-A8 : instruction fetch for dual-issue
    Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard  to reason why...
  • I am looking for a Cortex A8 evaluation board that has  32 bit ports
    I am looking for a Cortex A8 evaluation board that has  32 bit ports and USB port.   I am new to this and it may not be possible.   Do not need external memory or other peripherals, no operating system...