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  • VMSAv8-64 - How to change 2-stage translation table descriptors of a given VMID and do invalidation afterwards?
    Hello everyone, Basically, I have a setup in which an hypervisor is running in EL2 and two guestOS running in EL1/EL0, being one a special guest (able to perform requests to the hypervisor), and the...
  • page table Cachability bit effect!
    Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
  • Correct usage of the NSTable bit in aarch64/armv7a LPAE
    I'm porting our armv7a-short descriptor OS to LPAE and aarch64. In the short descriptor MMU, the "NS" bit can only be found in the first level of the MMU (I'll call it the SECTION level), meaning that...
  • How NS bit is set in case of DMA transfer ?
    Hi, When core makes a transaction, NS signal is sent on AXI bus depending on the SCR.NS bit. But when DMA transaction is issued, how the NS bit is propagated on the AXI bus ? Thanks Sahil