• aarch64 kernel using aarch32 page tables
    Hi ! I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8. My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point...
  • Question about LPAE(Large Physical Address Extensions) for ARMv7
    I read the ARMv7 architecture reference manuals. The spec. says LPAE allows 32-bits VA to be translated into 40-bits PA. The 40-bits PA means the width of address bus is 40-bits or greater than 40 bits...
  • MMU - Permission Fault with EL1 access
    Hello everyone, I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal). I've successfully...
  • Does the ThunderX CP processor support AArch32?
    It's my understanding that AArch64 is supposed to be backward compatible with AArch32, at least that is what the documentation says. But, I found one (1) page at https://en.wikichip.org/wiki/cavium/thunderx...
  • Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
    Hello: Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess...