• Can we reset L2 subsystem for cortex-A57?
    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running...
  • How to configure Cortex-A57 PMU
    I asked this question in a different community space but it seemed like this is a more appropriate home. I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The...
  • Processor Modes in cortex-A57
    Hi, I have done some basic assembly in Armv7-A processors (cortex A9). The version of ARM supports modes like User, sys, SVC etc. Does the ARMv8 also has the similar modes? Where can i find the details...
  • CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM
    hi, experts:  In Cortex-A57 TRM chapter 4.3.66 : It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1. Its name is S3_1_C15_C2_0. Why? best wishes, hi
  • trustzone memory configuration for cortex-A57
    Hello, I am using jetson tx2 development board which has arm cortex a57 processor which uses arm trusted firmware(atf) to boot. Trusty is the secure world operating system provided by atf. Following...