• ARMv7 Vs ARMv8 AArch32 Performance improvement
    Hello, I'm using an ARMv8 processor in 32 bit ARMv7 compatibility mode. I would like to know if there is any difference (performance gain) in ARMv8 running in AArch32 mode Vs running the same on an...
  • What is the effect of LDR r0, [r5, r6, LSL r2]
    It's actually written like this: LDR r0 , [r5, r6, LSL r2]...The first r0 is bolded. What does that mean (if anything)? Is there also a difference if it's written as "R0" instead of "r0"? My textbook...
  • page table Cachability bit effect!
    Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
  • why some instructions are not required to be  explicitly synchronized ?
    Dear all: In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions , it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need...
  • Cryptography instructions sample for ARMv8
    hi, experts: I found ARMv8 supported some cryptography instructions. So: Is there any sample code demonstrating how to use these crypto instructions? best wishes,