• PMU's cycles counter showing unstable values
    I'm trying to measure performance of my code by using pmu. Code placed in EL1. To test pmu I created simple loop of couple operations. I did it under spinlock with disabled interrupts to prevent any preemption...
  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?
    Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...
  • Event counters take differing number of cycles
    We have some code that sets up various event counters and reads them.  We bracket this code with reads of the cycle counter.  We have noticed that depending on what event counter we are configuring, we...
  • ARM PMU access DRAM Event
    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf pagina 243, what event number i neet to select to count all the DRAM access (read / write)?
  • Armv7 ICIALLU vs ICIALLUIS
    Hi experts! I have a question about cache instruction. DDI0406C_b_arm_architecture_reference_manual for Armv7  says Effect of the Multiprocessing Extensions on All and set/way maintenance operations The...