• BURST option in AHB-to-AHB sync-up bridge
    Hello, I am looking at cmsdk_ahb_to_ahb_sync_up.v component with BURST option enabled. I wonder how the BURST transfers are treated by this AHB-to-AHB sync-up bridge in case of an ERROR response?...
  • Memory controller for AHB, dual (or multi) channel
    Hi, I am looking for a memory controller for AHB, dual (or multi) channel. I found one in the ARM site but for AXI. Thank you
  • In AHB, can i program HSPLITx signal from slave sequence
    Hi,     I have a scenario like 2masters firing write or read burst to different slave.      M1 ---> S1 (Slave S1 performs SPLIT response for any transfer of the burst )      M2 ---> S2 (Slave S2 performs...
  • How hsel behaves in AHB?? Relation with HWRITE ,HWDATA,HRDATA
    I wanted to know the relation b/w HWRITE and HSEL
  • How to deal with the AHB slave only supporting word access ?
    Hi there,   Here is an AHB slave module which only supports word access (HSIZE[2:0] = 3'b010).   I plan to put it in a SoC, in which masters and interconnect could  launch byte, half-word and word transcation...