• shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • shareability memory attribute
    Hi ARM experts,     For shareability attribute, have some confusions:     1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?
    Hi, I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores. The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters...
  • indirect branches in ARMv8
    Please clarify that with me... With "The current Program Counter (PC) cannot be referred to by number as if part of the general register file and therefore cannot be used as the source or destination...
  • Using shareable attribute in MPU configuration of Cortex R4
    Good day all, I'm working with a SOC with dual Cortex-R4 that comes with MPU. Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS. Currently I'm working...