• Cortex M4: Atomic and Cache
    Hello all, Recently I came across this issue for the cortex M4 core. We are running a freertos application which loads and stores the value of a variable. For this we are using the atomic functions...
  • Why do we need atomicity in ARM Architecture?
    How does atomicity work with the memory accesses?
  • How to test atomic access implemented with Load Store Exclusive Assembly (LDREX / STREX)
    Hi there, i have several inline assembly functions wrapped in C. They implement atomic / read-modfy-write style Compare And Swap Increment Decrement Lock Semaphore Creating a good...
  • v8.2 Atomic Instructions
    Hello, In the new v8.2, atomic instructions are presented which can be an alternative to the previous ld/st exclusive and other similar instructions. My question is what is the advantage of using...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...