• why inner attribute is affected by outer configuration?
    Hi expert: I am configuring a CortexA15 system. In the LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0 which is used by stage 1...
  • GIC V2: Interrupt ID 1023 -> race condition. How to prevent?
    Dear specialists, I have read the " ARM ® Generic Interrupt Controller Architecture version 2.0 Architecture Specification" very carefully and I have still troubles how to understand why an interrupt...
  • shareability attribute for armv8 cortex a-53
    Hi, I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512. My question is how...
  • Regarding mismatched memory attributes and cacheability
    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...
  • Detect if Interrupt Happened
    I am wondering if there is a way to detect if an interrupt occurred in section of code. I know in the M3/M4/M7 I can use the LDREX/STREX to see if an exception(interrupt) occurred, is there any other...